1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and more particularly to a flash memory.
2. Description of the Related Art
Nonvolatile semiconductor memories (for example, flash memories) have been incorporated into various electronic devices because they allow high packing densities.
Therefore, the demand has increased for further scaling down the dimensions of devices used in and increasing the operational reliability of the flash memories (see, for example, U.S. Pat. App. No. 2005/0083744).
In general, the flash memories are structured such that adjacent transistors share their source/drain regions. That is, the drain of a select gate transistor which is adjacent to the source of a memory cell transistor serves as the source of that cell transistor.
In such a structure, gate-induced drain leakage (GIDL) occurs at the drain of the select gate transistor adjacent to the memory cell transistor at the non-writing time (“1” programming time) of the cell transistor when the select gate transistor is placed in the off state.
After that, a write voltage is applied to a control gate electrode (word line). This write voltage is also applied to memory cell transistors (“1” programming cells) which do not need to be written to because the control gate electrode is common to memory cell transistors which are adjacent to one another in the row direction (x direction).
Even if the memory cell transistor connected to the drain of the select gate transistor is a “1” programming cell, therefore, there is the possibility that hot electrons resulting from the GIDL are drawn by the write voltage without extinction and then injected into the floating gate electrode. As a result, erroneous writing to the memory cell transistor occurs.
Such erroneous writing due to hot electrons has become remarkable as the dimensions of memory cells have been scaled down and hence the gate spacing has become reduced. In flash memories in which one memory cell has two or more thresholds as with multi-level flash memories, this problem will result in failure to perform precise threshold voltage control, lowering the reliability.